1. Field of the Invention
This invention relates to a method of forming a dual damascene via, in particular to a method of forming a dual damascene via by using a metal hard mask layer to prevent the via being connected with others vias to cause the leakage defects after forming the shape of the via.
2. Description of the Prior Art
In the manufacturing of devices on a semiconductor wafer, it is now the practice to fabricate multiple levels of conductive (typically metal) layers above a substrate. The multiple metallization layers are employed in order to accommodate higher densities as device dimensions shrink well below the one-micron design rules. Likewise, the size of inter-connective structures will also need to shrink, in order to accommodate the smaller dimensions. Thus, as integrated circuit technology advances into the sub-0.25 micron range, more advanced inter-connective architecture and new materials are required.
One such architecture is a dual damascene integration scheme in which a dual damascene structure is employed. The dual damascene process offers the advantage in process simplification by reducing the process steps required to form the vias and trenches for a given metallization level. The openings, for the wiring of a metallization level and the underlying via connecting the wiring to a lower metallization level, are formed at the same time. The procedure provides an advantage in lithography and allows for improved critical dimension control. Subsequently, both the via and the trench can be filled utilizing the same metal-filling step, thereby reducing the number of processing steps required. Because of the simplicity of the dual damascene process, newer materials can cost-effectively replace the use of the existing aluminum (Al)/SiO2 (silicon dioxide) scheme.
Referring to FIG. 1, this shows a diagram in forming the shape of the dual damascene via by using the traditional method. When the dual damascene via is formed by using the traditional method, a wafer, which comprises the first metal layer 10, a cap layer 20, the first low dielectric constant dielectric layer 30, a middle etching stop layer 40, the second low dielectric constant dielectric layer 50, the first hard mask layer 60, and the second hard mask layer 70, is must provided at first. The second step is to decide a location of an isolation layer on the second hard mask layer 70 and to form the second hard mask layer 70 on the isolation layer by using a photolithography and a etching procedure to remove the partial second hard mask layer 70. The third step is to form the first trench in the second low dielectric constant dielectric layer 50 and the middle etching stop layer 40 by using the photolithography and the etching procedure to remove the partial middle etching stop layer 40 and the partial second low dielectric constant dielectric layer 50. The fourth step is to form the second trench in the first low dielectric constant dielectric layer 30 and the cap layer 20 by using the photolithography and the etching procedure to remove the partial first low dielectric constant dielectric layer 30, the partial middle etching stop layer 40, and the partial cap layer 20. The first trench and the second trench can be connected with each other to become the shape of the dual damascene via. The isolation layer, which is used to isolate the dual damascene via, is combined by using the middle etching stop layer 40, the second low dielectric constant dielectric layer 50, the first hard mask layer 60, and the second hard mask layer 70.
Referring to FIG. 2, after forming the shape of the dual damascene via on the wafer, a metal layer 80 is formed in the dual damascene via and filled of the dual damascene via. Then the surface of the wafer will become a planar surface by proceeding a chemical mechanical polishing procedure and the dual damascene via procedure is finished.
In the traditional dual damascene via procedure, in order to prevent the first low dielectric constant dielectric layer 30 and the second low dielectric constant dielectric layer 50 being affected by the stress, which is produced in the chemical mechanical polishing procedure, to cause the deformation defect or contacting with the slurry directly to change properties of the first low dielectric constant dielectric layer 30 and the second low dielectric constant dielectric layer 50, there are one to three dielectric layers must being formed on the second low dielectric constant dielectric layer 50 to eliminate the influence of the stress and to avoid the changes of the properties. These one to three dielectric layers are the first hard mask layer 60 and the second hard mask layer 70. But in the present procedure, the selective etching rate among the first hard mask layer 60, the second hard mask layer 70, the first low dielectric constant dielectric layer 30, and the second low dielectric constant dielectric layer 50 is not enough. Therefore, the first hard mask layer 60 and the second hard mask layer 70 will usually have the rounding profile after finishing the etching procedures from the second step to the fourth step. This rounding profile will decrease the distance between the dual damascene vias and decrease the process window in the back-end chemical mechanical polishing procedure. This rounding profile will also produce the bridging defect between the dual damascene vias more easily to cause the leakage defect. This rounding profile will further decrease the qualities of the semiconductor device and will increase the cost of the procedure.
In accordance with the background of the above-mentioned invention, the traditional method will produce the rounding profile on the surface of the isolation layer easily to affect the process window of the back-end procedure and to produce the bridging defect between the dual damascene vias easily to cause the leakage defect. The present invention provides a method of forming the dual damascene via by using the metal layer to be the hard mask layer to make the surface of the isolation layer, which is between the dual damascene vias, become a level and smooth surface to avoid the bridging defect, which is produced between the dual damascene vias.
The second objective of this invention is avoid the leakage defect, which is produced between the dual damascene vias, by using the metal layer to be the hard mask layer to make the surface of the isolation layer, which is between the dual damascene vias, become a level and smooth surface.
The third objective of this invention is to increase the process window in the back-end procedure by using the metal layer to be the hard mask layer to make the surface of the isolation layer, which is between the dual damascene vias, become a level and smooth surface.
The fourth objective of this invention is to increase the qualities of the semiconductor device by using the metal layer to be the hard mask layer to make the surface of the isolation layer, which is between the dual damascene vias, become a level and smooth surface.
The further objective of this invention is to decrease the cost of the procedure by using the metal layer to be the hard mask layer to make the surface of the isolation layer, which is between the dual damascene vias, become a level and smooth surface.
In according to the foregoing objectives, the present invention provides a method of forming the dual damascene via by using the metal layer to be the hard mask layer to make the surface of the isolation layer, which is between the dual damascene vias, become a level and smooth surface to avoid the bridging defect, which is produced between the dual damascene vias. The present invention will also avoid the leakage defect, which is produced between the dual damascene vias and to increase the width of the procedure in the back-end procedure. The present invention will further increase the qualities of the semiconductor device and decrease the cost of the procedure.